Messaging, sequences, register layer and other features enhanced in successful standard
Napa, Calif., USA, 24 June 2014 - Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced it released a new version of its Universal Verification Methodology (UVM) class reference document, UVM 1.2 for SoC (system on chip) verification. UVM 1.2 improves interoperability and reduces the cost of IP development and reuse for each new project. The new version includes enhanced messaging, improvements to the register layer and other features. UVM 1.2 and its reference implementation are available for download under Apache 2.0 open source license at www.accellera.org.
"The UVM working group has achieved the goals of its charter to enhance SoC productivity throughout the industry," said Tom Alsop, UVM Working Group co-chair. "We are proud to report that UVM 1.2 continues the work to define new features and improve quality of the reference implementation."
UVM has attracted immense interest worldwide with an active user community and forum. The LinkedIn group now tops 5,000 members. The reference implementation includes detailed release notes and a script to help users upgrade as some of the new features do introduce backward incompatibility. Some of the new features include:
Messaging is now object-oriented enabling users to extend the built-in features
Sequences can automatically raise and drop objections for improved sequence control
The register layer can now control transaction order within bursts simplifying the verification of complex protocols
Reference implementation quality is enhanced with numerous bug fixes
Public Review Invites User Participation
UVM 1.2 is entering a three-month review period ending October 1, 2014 with a commitment to take the resulting updated UVM 1.2 standard to the IEEE. Users are encouraged to post comments and suggestions using the UVM 1.2 Public Review Forum. A technical tutorial from the 2014 Design and Verification Conference is available to users and includes an introduction to the standard as well as in-depth user details on the new features of UVM 1.2.
About Accellera Systems Initiative
Accellera Systems Initiative is an independent, not-for profit organization, dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org. For membership information, please contact us.
Accellera, Accellera Systems Initiative, and UVM are trademarks of Accellera Systems Initiative Inc. All other trademarks and trade names are the property of their respective owners.