Cadence Quantus QRC Extraction Solution Certified for TSMC 16nm FinFET

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SAN JOSE, Calif., 14 Jul 2014

Highlights:

  • Quantus QRC Extraction solution passes rigorous parasitic extraction certification requirements in TSMC 16nm FinFET
  • Delivers best-in-class 16nm functionality, accuracy, performance, and post-layout simulation and characterization runtimes to support FinFET designs
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that TSMC has certified Cadence Quantus QRC Extraction solution for TSMC 16nm FinFET. Cadence Quantus QRC Extraction Solution successfully passed TSMC’s rigorous parasitic extraction certification requirements to achieve best-in-class accuracy against the foundry golden data for FinFET technology.

At 16nm, there are new modeling challenges, including the introduction of FinFET 3D device structures, with more complex parameters for parasitic capacitance and resistance. These challenges require the highest accuracy in signoff extraction. Quantus QRC Extraction solution is able to meet these challenges using its robust modeling infrastructure to deliver the highest accuracy models, and produce the smallest netlist to enable faster simulation and characterization runtimes.

“The certification of Quantus QRC Extraction solution by TSMC is the result of close collaboration between both companies’ R&D teams to accurately model complex parasitic effects to address the new challenge of FinFET devices,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “We are delighted to see Quantus QRC Extraction delivers the solution for FinFET designs that meet TSMC’s certification requirements and will continue our collaboration with Cadence on future technologies.”

“With Quantus QRC Extraction solution, our customers can reduce their design closure turnaround time by removing the extraction performance bottleneck in the digital and custom/analog electrical signoff flow,” said Anirudh Devgan, senior vice president of the Digital & Signoff Group at Cadence. “With the introduction of this new extraction solution and certification by TSMC at 16nm FinFET designs, Cadence now offers a significantly differentiated solution for digital, and custom/analog designs.”

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.


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