State aid: Commission approves €400 million aid to STMicroelectronics for the Nano2017 research programme
The European Commission has decided that aid by France to STMicroelectronics (ST) for the development of new technologies in the nanoelectronics sector is in line with EU rules on state aid. It believes the project will help to achieve EU targets in the field of science and the environment without unduly distorting competition.
Commission Vice-President in charge of competition policy, Joaquín Almunia, said: "The aim of the Nano2017 programme is to make major advances inthe field of nanoelectronics. It offers a new European dimension that will boost synergies between the three major European clusters and establish a structure for the sector. Once more, our decision shows that the monitoring of state aid does not in any way impede modern and forward-looking industrial policies, but is a way of investing effectively in the key sector of research, innovation and development."
At the end of 2013, France notified the Commission of its plans to give aid to ST for implementing the Nano2017 programme. The aim of the programme is to develop new technologies for the design and production of the next generation of integrated circuits and to strengthen the structure of the European micro- and nanoelectronics industry by positioning the Crolles-Grenoble cluster as a global leader in the field of advanced CMOS (Complementary Metal-Oxide-Semiconductor) technology.
The programme is being implemented by a consortium of 174 partners from 19 countries across Europe (62 of which belong to the 3 major European clusters) led by ST. It will be partly financed by the ENIAC Joint Undertaking (in particular, new pilot-line projects for key enabling technologies) and thus forms an integral part of the objectives of Horizon 2020, the new EU programme for research and innovation (http://ec.europa.eu/programmes/horizon2020/).
The Commission examined the aid in the light of its framework for state aid for research and development and innovation (R&D&I, see IP/06/1600 and MEMO/06/441) and concluded that the aid would remedy market failures. It will improve coordination both among companies in the sector, and between companies and research bodies, making it possible for the results of the project to be disseminated widely through scientific publications and training programmes. It will also enable European suppliers of the semiconductor industry (parts manufacturers, support services, substrate suppliers) to continue developing a state-of-the-art R&D and production infrastructure in Europe, allowing them to design innovative solutions that are tailored to the most advanced technologies. The research will focus on devising ways to reduce the power consumption of components. The Commission concluded that the aid would have a positive effect on the value chain and would allow major energy savings to be made in the future.
The Commission also checked that the aid was both necessary and sufficient to prompt ST to embark on an R&D project that it would not otherwise have undertaken (no deadweight effect). Given the openness of the upstream technology markets and the beneficiary’s limited market share in them, there was no risk that competition would be distorted.
Nanoelectronics is a ‘key enabling technology’ underlying innovation in many branches of industry. The global semiconductor market (worth around € 231 billion in 2010) impacts not only markets downstream of the electronics sector (around € 1162 billion) and related services (around € 5174 billion) but also the markets for nanoelectronics production equipment and materials. Semiconductors are omnipresent both in industries traditionally associated with microelectronics and elsewhere too (very high-speed communications accessible to all, cloud computing, smart power grids, e-health, network security, intelligent transport systems, etc.).
The pace of technological progress in microelectronics is very rapid, with ever more highly integrated technologies emerging every 18 to 24 months, leading in turn to a new generation of products appearing on the market every six months and a steady fall in production costs. Each new stage (‘ technology node’) is referred to by the typical feature size — currently 32/28 nm in industrial production and development, 22/20 nm in industrial R&D, and 10 nm in the advanced research phase, with preliminary studies of 7 and 5 nm technology under way in basic research laboratories.
Two technologies currently make it possible to scale down beyond 28 nm: (1) FinFET technology, created by the DARPA laboratories in the United States and first produced industrially by Intel, then later by TSMC; and (2) FDSOI (Fully Depleted Silicon on Insulator) technology. The ISDA alliance with IBM and the Nano2012 project have demonstrated FDSOI’s performance and its potential to replace CMOS transistors on massive substrates for 28 nm technology (see IP/09/150); developing it beyond 28 nm is the core focus of the Nano2017 programme. Nano2017 aims to reposition FDSOI technology as an alternative to FinFET technology on the global market.
The public version of the decision will be made available under case number SA.37743 in the State Aid Register on the DG Competition website once any confidentiality issues have been resolved. The electronic newsletter ‘State Aid Weekly e-News’ lists the most recent decisions on state aid published in the Official Journal and on the internet.