FlexLine™ is a significant paradigm shift from conventional wafer level manufacturing with unprecedented flexibility and cost advantages
Singapore – 11 March 2014 – STATS ChipPAC Ltd. (“STATS ChipPAC” or the “Company” – SGX-ST: STATSChP), a leading provider of advanced semiconductor packaging and test services, has designed and implemented an innovative new manufacturing method that is a significant paradigm shift from conventional wafer level manufacturing. This breakthrough approach, known as FlexLine™, delivers an unmatched level of flexibility and cost savings for wafer level packaging (WLP).
With conventional WLP, an integrated circuit (IC) is fabricated, packaged and tested while still in a wafer format to streamline the manufacturing process. WLP leverages the same semiconductor equipment infrastructure as wafer fabrication which is progressively more expensive for larger wafer diameters and finer silicon (Si) geometries. The costs associated with transitioning to larger wafer diameters have resulted in extreme pricing pressures on WLP, particularly for mature technology such as wafer level chip scale packaging (WLCSP).
“Growing demand for WLCSP in a range of advanced mobile products, from low-cost to high-end smartphones and tablets, is driving capacity constraints in the industry, particularly with 200mm wafers. This is causing extreme pressure on our customers to weigh the high cost of transitioning to more advanced silicon nodes against the need to achieve dramatic cost reductions for more competitive end products,” said Chong Khin Mien, Senior Vice President of Product and Technology Marketing, STATS ChipPAC. “Capacity and cost challenges for WLCSP exist today in 200mm and 300mm wafer diameters and will inevitably intensify when the semiconductor industry transitions to 450mm wafers. This is an exciting time to drive a fundamental change in the manufacturing process for WLCSP.”
STATS ChipPAC’s new FlexLine method is an innovative approach to wafer level manufacturing that provides freedom from wafer diameter constraints while enabling supply chain simplification and significant cost reductions that are not possible with a conventional manufacturing flow. FlexLine seamlessly processes multiple silicon wafer diameters in the same manufacturing line without changing equipment sets or bill of materials used in the packaging process. In fact, FlexLine enables customers to simplify their supply chain across multiple devices, thereby achieving significant cost reductions that are not possible with a conventional manufacturing flow.
“STATS ChipPAC is driving a significant paradigm shift in wafer level packaging with our FlexLine method. We have leveraged our proven reconstitution process, which has produced more than half a billion units of fan-out wafer level packages, to extend flexibility and cost advantages to fan-in WLCSP devices. We are the first company in the world to introduce a WLP method that is completely independent of incoming wafer sizes, including future 450mm wafer size, and delivers unprecedented flexibility in producing both fan-out and fan-in packages on the same manufacturing line,” said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC.
By normalising multiple wafer diameters to a uniform processing size through reconstitution, the original wafer diameters become irrelevant as this no longer dictates manufacturing capacity or limits process capabilities. When 200mm wafers are reconstituted into 300mm or larger panel sizes, customers have greater potential for cost reduction than conventional WLP manufacturing. As the panel size increases, the cost of producing wafer level packages drops significantly when compared to conventional WLP methods.
Dr. Han noted, “With FlexLine™, we are able to help our customers achieve at least a 15-30% cost reduction using the optimum design requirements for their WLCSP devices. Later this year we will introduce unique technology enhancements to WLCSP that improve the reliability performance over WLCSPs produced with conventional methods. Our FlexLine™ method provides a strong manufacturing platform that enables future innovation in our wafer level packaging portfolio.”
Certain statements in this release are forward-looking statements that involve a number of risks and uncertainties that could cause actual results to differ materially from those described in this release. Factors that could cause actual results to differ include, but are not limited to, general business and economic conditions and the state of the semiconductor industry; prevailing market conditions; demand for end-use applications products such as communications equipment, consumer and multi-applications and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; level of competition; our reliance on a small group of principal customers; our continued success in technological innovations; pricing pressures, including declines in average selling prices; intellectual property rights disputes and litigation; our ability to control operating expenses; our substantial level of indebtedness and access to credit markets; potential impairment charges; availability of financing; changes in our product mix; our capacity utilisation; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; returns from research and development investments; changes in customer order patterns; customer credit risks; disruption of our operations; shortages in supply of key components and disruption in supply chain; inability to consolidate our Malaysia operations into our China operations and uncertainty as to whether such plan will achieve the expected objectives and results; loss of key management or other personnel; defects or malfunctions in our testing equipment or packages; rescheduling or cancelling of customer orders; adverse tax and other financial consequences if the taxing authorities do not agree with our interpretation of the applicable tax laws; classification of our Company as a passive foreign investment company; our ability to develop and protect our intellectual property; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; majority ownership by Temasek Holdings (Private) Limited (“Temasek”) that may result in conflicting interests with Temasek and our affiliates; unsuccessful acquisitions and investments in other companies and businesses; labour union problems in South Korea; uncertainties of conducting business in China and changes in laws, currency policy and political instability in other countries in Asia; natural calamities and disasters, including outbreaks of epidemics and communicable diseases; the continued trading and listing of our ordinary shares on the Singapore Exchange Securities Trading Limited (“SGX-ST”). You should not unduly rely on such statements. We do not intend, and do not assume any obligation, to update any forward-looking statements to reflect subsequent events or circumstances.
About STATS ChipPAC Ltd.
STATS ChipPAC Ltd. (SGX-ST Code: S24) is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions in diverse end market applications including communications, digital consumer and computing. With global headquarters in Singapore, STATS ChipPAC has design, research and development, manufacturing or customer support offices throughout Asia, the United States and Europe. STATS ChipPAC is listed on the SGX-ST. Further information is available at www.statschippac.com. Information contained in this website does not constitute a part of this release.